chip-scale

Labels: chip-scale integration, darpa, mr fusion posted by dubjay at 7:20 PM

Archive 2009-07-01 Walter Jon Williams 2009

Labels: chip-scale integration, darpa, mr fusion posted by dubjay at 7:20 PM

Meet Mr Fusion Walter Jon Williams 2009

The packaging is insane: chip-scale fully hidden connectivity, package pithces of a few 100 microns.

Boing Boing: April 20, 2003 - April 26, 2003 Archives 2003

Our projects span the space between very applied work on devices like ultra-low voltage electrooptic modulators, to interest in chip-scale nonlinear and quantum optics for novel light sources and all-optical logic circuits.

The Seattle Times 2011

The company's micro-electronics solutions enable smaller, higher-functionality devices through chip-scale, 3D and wafer-level packaging technology, as well as high-density substrate and silent air cooling technology.

Tessera to Present at Photonics West - Yahoo! Finance 2011

ADP5034 regulator/LDO, a highly integrated power management IC that combines two 3-MHz, high efficiency, 1.2-A step down regulators with two 300-mA LDO (low drop out) regulators in a small LFCSP (lead-frame chip-scale) package.

unknown title 2011

Our chip-scale packages were down 9% due to weakness in wireless base band chips as Ken discussed.

unknown title 2011

The idea behind OpSIS - "optoelectronic systems integration in silicon" - is to help engineers and researchers working on different projects to share the cost of fabricating chip-scale systems.

The Seattle Times 2011

The company's micro-electronics solutions enable smaller, higher-functionality devices through chip-scale and wafer-level packaging technology, silicon-level interconnect and 3-D packaging, as well as silent air cooling technology.

unknown title 2011

Measuring 12 mm2, the AR6005's chip-scale package can be easily implemented in the thinnest mobile devices.

unknown title 2011