clock-gating

The suite also provides advances in timing-driven design preservation, 'intelligent' clock-gating technology that reduces dynamic power consumption by up to 30 per cent and a design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a range of high-performance applications.

Electronicstalk - electronics industry news 2010

Identifies design regions using PowerPro generated statistics (power, clock-gating efficiency, toggle data, etc.) where micro-architectural modifications would result in identification of additional clock gating/memory gating opportunities by PowerPro.

EDA Blog 2010

Xilinx then applied innovative architectural enhancements to lower dynamic power consumption both for logic and I/O, while also introducing intelligent clock-gating technology with the release of ISE Design Suite 12.

Embedded Computing Design Xilinx 2010

ISE Design Suite 12's clock-gating technology includes fully automated analysis and fine-grain (logic slice) optimisation capabilities that have been developed to reduce the number of transitions.

Electronicstalk - electronics industry news 2010

This approach will definitely consume fewer buffers compared with the results of using buffered clock-gating cells.

unknown title 2009

Usually designers decide clock-gating strategy during synthesis.

unknown title 2009

For each clock-gating cell replaced, the number of muxes coming back into the picture is the same as the number of flops the clock-gating cell was gating.

unknown title 2009

So we in effect assume that the clock on the flop that launches the enable signal is coincident with the clock coming into the clock-gating cell.

unknown title 2009

So when we remove these clock-gating cells, the muxes take their original place.

unknown title 2009

Normal scan testing requires bypassing the clock-gating cells in the design.

unknown title 2009