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Examples
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The Tower System provides a common development platform for Power Architecture devices that range in performance from 60 to 2550 Dhrystone million instructions per second DMIPS.
unknown title 2011
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Dhrystone 2 using register variables 116700.0 36339320.2 3113.9
Digital Point Forums 2010
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By enhancing the pipeline structure of the company's existing V850E2 CPU core, Renesas has strengthened the parallel processing capability required for demanding environments and successfully developed the V850E2M core with processing performance of 2.56 Dhrystone MIPS per MHz per core, increased by 1.4 times from the company's previous
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Processor (Dhrystone (MIPS), Whetstone (MFLOPS), Mandelbrot fractal ...)
Warp2Search.net 2010
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Dhrystone MIPS at a clock speed of 200MHz, the MCUs have two built-in CPU cores, 64KB of random access memory (RAM) available for each core, 2MB of flash memory and an additional 64KB system RAM available in a 304-pin fine-pitch ball-grid array (FBGA) package.
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Dhrystone 2 using register variables 12398026.2 lps (10.0 s, 7 samples)
Digital Point Forums 2010
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Dhrystone (MIPS) - higher results are better, i.e. better integer performance.
OCTools 2010
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Dhrystone 2 using register variables 116700.0 12398026.2 1062.4
Digital Point Forums 2010
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Dhrystone 2 using register variables 36339320.2 lps (10.0 s, 7 samples)
Digital Point Forums 2010
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CPUs in system; running 4 parallel copies of tests Dhrystone 2 using register variables 36351495.2 lps (10.0 s, 7 samples)
Digital Point Forums neo1211 2010
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